Field of the Invention
Embodiments of the present invention relate generally to data interconnects and, more specifically, to a technique for scaling the bandwidth of a processing element to match the bandwidth of an interconnect.
Description of the Related Art
A conventional computing device typically includes various processing units coupled together via a high-speed interconnect. The processing units are configured to exchange data with one another across the high-speed interconnect according to different clock signals that drive the high-speed interconnect and the processing units. Conventional high-speed interconnects typically operate at a specific clock rate that may not be easily scaled down. Older processing units typically operate at a clock rate that can be matched to the clock rate associated with the high-speed interconnect.
However, modern processing units may operate with variable clock rates under different operating conditions. For example, a central processing unit (CPU) within a mobile device may operate with a lower clock rate when processing demands are relatively low in order to conserve power. Such functionality may present a mismatch between the specific clock rate of the high-speed interconnect, and the variable clock rate of the processing units to which that interconnect is coupled. Consequently, the high-speed interconnect may, at times, deliver more bandwidth to a given processing element than the processing element can receive.
One solution to the problem described above is to configure the processing unit to buffer all incoming data, and to then read that data with the clock rate of the processing unit. However, this solution may require large buffers, and even so, those buffers may overrun. To prevent buffer overrun, the processing unit may track buffer consumption, and then communicate with an upstream transmitter an amount of data to send that will fit into the buffer. However, this solution can be complex and unwieldy.
Accordingly, what is needed in the art is a technique for mitigating a bandwidth mismatch between a processing element and an interconnect.